The present invention relates to a semiconductor device having a seal ring structure surrounding a chip region and to a method for fabricating the device.
A semiconductor device is generally fabricated by arranging a large number of integrated circuits (ICs) constituted by a plurality of elements and provided with given functions on a semiconductor wafer of, for example, silicon.
A large number of chip regions arranged on a wafer are separated from each other by a scribe region (scribe line) having a lattice pattern. After the large number of chip regions have been formed on a wafer through a semiconductor fabrication process, the wafer is diced into chips along the scribe region, thereby forming semiconductor devices.
However, when the wafer is diced into chips, chip regions near the scribe line might suffer mechanical damage, resulting in occurrence of cracks or chipping in part of the diced cross sections of the separated chips, i.e., semiconductor devices.
To solve this problem, in Japanese Unexamined Patent Publication (Kokai) No. 2001-23937 (hereinafter, referred to as reference 1), proposed is a technique for preventing crack propagation in chip regions during dicing by providing a seal ring serving as a ring-shaped protection wall around the chip regions.
FIG. 19 is a cross-sectional view showing a conventional semiconductor device (formed in a wafer) having a seal ring.
As shown in FIG. 19, a chip region 2 is defined in a of a wafer by a scribe region 3. A multilayer structure made of a plurality of interlayer dielectric films 5 through 10 is formed on the substrate 1. An active layer 20 constituting an element is formed in the substrate 1 in the chip region 2. A plug (via) 21 is formed through the interlayer dielectric film 5 to be connected to the active layer 20. An interconnect 22 is formed through the interlayer dielectric film 6 to be connected to the plug 21. A plug 23 is formed through the interlayer dielectric film 7 to be connected to the interconnect 22. An interconnect 24 is formed through the interlayer dielectric film 8 to be connected to the plug 23. A plug 25 is formed through the interlayer dielectric film 9 to be connected to the interconnect 24. An interconnect 26 is formed through the interlayer dielectric film 10 to be connected to the plug 25.
As shown in FIG. 19, in part of the multilayer structure of the interlayer dielectric films 5 through 10 located in a peripheral part of the chip region 2, a seal ring 4 is formed through the multilayer structure to completely surround the chip region 2. As shown in reference 1, for example, the seal ring 4 is formed by alternately using masks for forming interconnects and masks for forming vias. Specifically, the seal ring 4 includes: a conductive layer 30 formed in the substrate 1; a seal via 31 formed through the interlayer dielectric film 5 to be connected to the conductive layer 30; a seal interconnect 32 formed through the interlayer dielectric film 6 to be connected to the seal via 31; a seal via 33 formed through the interlayer dielectric film 7 to be connected to the seal interconnect 32; a seal interconnect 34 formed through the interlayer dielectric film 8 to be connected to the seal via 33; a seal via 35 formed through the interlayer dielectric film 9 to be connected to the seal interconnect 34; and a seal interconnect 36 formed through the interlayer dielectric film 10 to be connected to the seal via 35. Parts of the seal ring formed by using masks for forming interconnects will be hereinafter referred to as seal interconnects, and parts of the seal ring formed by using masks for forming vias will be hereinafter referred to as seal vias.
As shown in FIG. 19, a passivation film 11 is formed on the multilayer structure of the interlayer dielectric films 5 through 10 in which interconnects (22, 24, 26), vias (21, 23, 25) and the seal ring 4 are provided. The passivation film 11 has an opening on the interconnect 26, and a pad 27 connected to the interconnect 26 is formed in the opening.